Fault simulation and response compaction in full scan circuits using HOPE

S.R. Das, M.H. Assaf, E.M. Petriu, W.-B. Jone
IMTC/2002. Proceedings of the 19th IEEE Instrumentation and Measurement Technology Conference (IEEE Cat. No.00CH37276)  
This paper presents results on fault simulation and response compaction on ISCAS 89 full scan sequential benchmark circuits using HOPE-a fault simulator developed for synchronous sequential circuits that employs parallel fault simulation with heuristics to reduce simulation time in the context of designing space-efficient support hardware for built-in self-testing of very large-scale integrated circuits. The techniques realized in this paper take advantage of the basic ideas of sequence
more » ... rization previously developed and utilized by the authors for response data compaction in the case of ISCAS 85 combinational benchmark circuits, using simulation programs ATALANTA, FSIM, and COMPACTEST, under conditions of both stochastic independence and dependence of single and double line errors in the selection of specific gates for merger of a pair of output bit streams from a circuit under test (CUT). These concepts are then applied to designing efficient space compression networks in the case of full scan sequential benchmark circuits using the fault simulator HOPE. Index Terms-Built-in self-test (BIST), circuit under test (CUT), detectable error probability estimates, fault simulation using HOPE, Hamming distance, optimal sequence mergeability, response compaction, sequence weights, single stuck-line faults, space compactor.
doi:10.1109/imtc.2002.1006911 fatcat:vlkkue6udzevjaa6j7rxpsfzn4