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In this paper, we present the design and experimental evaluation of an 8-bit adiabatic multiplier with built-in self-test (BIST) logic and an internal single-phase sinusoidal power-clock generator. Both the multiplier and the BIST have been designed in SCAL-D, a true single-phase adiabatic logic family. In HSPICE simulations with post-layout extracted parasitics, our design functions correctly at frequencies exceeding 200 MHz, with total dissipation for the multiplier and BIST circuitry of 91pJdoi:10.1109/arvlsi.2001.915549 dblp:conf/arvlsi/KimZP01 fatcat:ztvlxe6sxzcxzpxlrmzj26e3c4