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Accelerating Image Algorithm Development using Soft Co-Processors on FPGAs
2018 29th Irish Signals and Systems Conference (ISSC)
FPGAs can offer high performance with low power and low hardware usage. However, with current software, FPGAs are hard to program, and lengthy re-synthesis times make them unsuitable for the algorithm experimentation which is typical of developing image processing applications. In this paper, we present a system model based on a set of Soft Co-Processors, each of which implements a basic image-level operation (or a common combination of such operations) based on the high-level operators indoi:10.1109/issc.2018.8585363 fatcat:vpvnkfcz5zgz5p32fltkltx4zq