Exploration and Customization of FPGA-Based Soft Processors

Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose
2007 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
As embedded systems designers increasingly use field-programmable gate arrays (FPGAs) while pursuing single-chip designs, they are motivated to have their designs also include soft processors, processors built using FPGA programmable logic. In this paper, we provide: 1) an exploration of the microarchitectural tradeoffs for soft processors and 2) a set of customization techniques that capitalizes on these tradeoffs to improve the efficiency of soft processors for specific applications. Using
more » ... infrastructure for automatically generating soft-processor implementations (which span a large area/speed design space while remaining competitive with Altera's Nios II variations), we quantify tradeoffs within soft-processor microarchitecture and explore the impact of tuning the microarchitecture to the application. In addition, we apply a technique of subsetting the instruction set to use only the portion utilized by the application. Through these two techniques, we can improve the performance-per-area of a soft processor for a specific application by an average of 25%. Index Terms-Customization, design space exploration, field--programmable gate array (FPGA)-based soft-core processors, processor generator. Peter Yiannacouras (S'06) received the B.A.Sc. degree from the Engineering Science Program at University of Toronto, Toronto, ON, Canada, and the M.A.Sc. degree from the Electrical and Computer Engineering Department at the same university, where he is currently working toward the Ph.D. degree. He has also worked with Intel Microarchitecture Research Labs. His research interests include processor architecture, embedded processing, fieldprogrammable gate array (FPGA) logic architecture, and automatic customization.
doi:10.1109/tcad.2006.887921 fatcat:gfpeul3d6bbxth65lanhaftlzi