Spanning graph-based nonrectilinear steiner tree algorithms

Qi Zhu, Hai Zhou, Tong Jing, X.-L. Hong, Yang Yang
2005 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
With advances in fabrication technology of very/ultra large scale integrated circuit (VLSI/ULSI), we must face many new challenges. One of them is the interconnect effects, which may cause longer delay and heavier crosstalk. To solve this problem, many interconnect performance optimization algorithms have been proposed. However, when these algorithms are designed based on rectilinear interconnect architecture, the optimization capability is limited. Therefore, nonrectilinear interconnect
more » ... ctures become a field of active research in which the octilinear interconnect architecture is the most promising one since it extends from the rectilinear case and greatly shortens the wire length. Meanwhile, an interconnect with less length is helpful to reduce wire capacitance, congestion, and routing area. In an interconnect architecture, the Steiner minimal tree (SMT) construction is one of the key problems. In this paper, we give two practical octilinear Steiner minimal tree (OSMT) construction algorithms based on octilinear spanning graphs (OSGs). The one with edge substitution (OST-E) has a worst-case running time of ( log ) and a similar performance as the recent work using batched greedy. The other one with triangle contraction (OST-T) has a small increase in the constant factor of running time and a better performance. These two are the fastest algorithms for octilinear Steiner tree construction so far. Experiments on both industrial and random test cases are conducted to compare with other programs. We also proposed the extension of our algorithms to any geometry. Index Terms-Deep submicron (DSM), interconnect, physical design, routing, Steiner tree, very large scale integration (VLSI).
doi:10.1109/tcad.2005.850862 fatcat:e5movnqpvzbtfisb4sqwtsqa6a