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Towards an H.264/AVC HW/SW Integrated Solution: An Efficient VBSME Architecture
2008
IEEE Transactions on Circuits and Systems - II - Express Briefs
This paper presents an efficient real-time variable block size motion estimation architecture. The proposed architecture provides motion vectors for each 16 16 block and its 40 sub-blocks. The proposed architecture is a single-instruction multiple-data architecture integrated with embedded SRAMs on one chip. The architecture has been prototyped using Xilinx Virtex-4 XC4VSX35-10 field-programmable gate array. It processes 30-CIF fps using 71-MHz clock frequency. Its maximum clock frequency is
doi:10.1109/tcsii.2008.923398
fatcat:gvqjdz6jtvh6njb46p35c2ul3i