Analysis of the Task Superscalar Architecture Hardware Design

Fahimeh Yazdanpanah, Daniel Jimenez-Gonzalez, Carlos Alvarez-Martinez, Yoav Etsion, Rosa M. Badia
2013 Procedia Computer Science  
In this paper, we analyze the operational flow of two hardware implementations of the Task Superscalar architecture. The Task Superscalar is an experimental task based dataflow scheduler that dynamically detects inter-task data dependencies, identifies task-level parallelism, and executes tasks in the out-of-order manner. In this paper, we present a base implementation of the Task Superscalar architecture, as well as a new design with improved performance. We study the behavior of processing
more » ... e dependent and non-dependent tasks with both base and improved hardware designs and present the simulation results compared with the results of the runtime implementation.
doi:10.1016/j.procs.2013.05.197 fatcat:dpb7gqgez5f6lh3e3fu565gxgy