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Analysis of the Task Superscalar Architecture Hardware Design
2013
Procedia Computer Science
In this paper, we analyze the operational flow of two hardware implementations of the Task Superscalar architecture. The Task Superscalar is an experimental task based dataflow scheduler that dynamically detects inter-task data dependencies, identifies task-level parallelism, and executes tasks in the out-of-order manner. In this paper, we present a base implementation of the Task Superscalar architecture, as well as a new design with improved performance. We study the behavior of processing
doi:10.1016/j.procs.2013.05.197
fatcat:dpb7gqgez5f6lh3e3fu565gxgy