Design for 32-Bit Parallel Polar Encoder Architecture

Praveen Kumar, Abhinav Ranjan, Hemanth Kumar
International Research Journal of Engineering and Technology   unpublished
This paper work is entirely focused on implementation of 32-bit polar encoder by using the algorithm based on FFT (Fast Fourier Transform) method. Associated theory of Polar code and related architecture and application is briefly described in this paper. In this paper FFT algorithm for constructing Polar Encoder is highlighted in one of subsection. Polar encoder design is mainly targeted for Xilinx spartan6 FPGA (field programmer gate array) and designed using Verilog HDL (Hardware Description
more » ... ardware Description Language). Simulation result of the designed 32-bit polar encoder (by using Verilog HDL) is taken using Xilinx ISE (Integrated Synthesis Environment) 14.2 tool.
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