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The ever increasing gap in processor and memory speeds has a very negative impact on performance. One possible solution to overcome this problem is the Kilo-instruction processor. It is a recent proposed architecture able to hide large memory latencies by having thousands of in-flight instructions. Current multiprocessor systems also have to deal with this increasing memory latency while facing other sources of latencies: those coming from communication among processors. What we propose, indoi:10.1145/1054943.1054953 dblp:conf/wmpi/GalluzziBPGCV04 fatcat:2r3xxn2qy5b4ppazmw5pc54wnm