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Control flow speculation in multiscalar processors
Proceedings Third International Symposium on High-Performance Computer Architecture
The Multiscalar architecture executes a single sequential program following multiple flows of control. In the Multiscalar hardware, a global sequencer, with help from the compiler, takes large steps through the program's control flow graph (CFG) speculatively, starting a new thread of control (task) at each step. This is inter-task control flow speculation. Within a task, traditional control flow speculation is used to extract instruction level parallelism. This is intra-task control flow
doi:10.1109/hpca.1997.569673
dblp:conf/hpca/JacobsonBSS97
fatcat:io2cowc5gzcknaxwtuji27qnsm