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An Executable Formal Model of the VHDL in Isabelle/HOL
[article]
2022
arXiv
pre-print
In the hardware design process, hardware components are usually described in a hardware description language. Most of the hardware description languages, such as Verilog and VHDL, do not have mathematical foundation and hence are not fit for formal reasoning about the design. To enable formal reasoning in one of the most commonly used description language VHDL, we define a formal model of the VHDL language in Isabelle/HOL. Our model targets the functional part of VHDL designs used in industry,
arXiv:2202.04192v1
fatcat:dkuhxolrcvfp7ckrlvbprnnpdi