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Low–Level Space Optimization of an AES Implementation for a Bit–Serial Fully Pipelined Architecture
[chapter]
2009
IFIP Advances in Information and Communication Technology
A previously developed AES (Advanced Encryption Standard) implementation is optimized and described in this paper. The special architecture for which this implementation is targeted comprises synchronous and systematic bit-serial processing without a central controlling instance. In order to shrink the design in terms of logic utilization we deeply analyzed the architecture and the AES implementation to identify the most costly logic elements. We propose to merge certain parts of the logic to
doi:10.1007/978-3-642-04284-3_25
fatcat:3rprr4ktj5eyni4pxipbe3zhzu