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Lecture Notes in Computer Science
Modern packet processing hardware (e.g. IPv6-supported routers) demands high processing power, while it also should be power-efficient. In this paper we present an architecture for high-speed packet processing with a hierarchical chip-level power management that minimizes the energy consumption of the system. In particular, we present a modeling framework that provides an easy way to create new networking applications on an FPGA based board. The development environment consists of a modelingdoi:10.1007/978-3-642-13971-0_4 fatcat:6lst5fvzynfk7ligkbrgg2wtom