Reduction of leakage current at the gate edge of SDB SOI NMOS transistor

Sung-Weon Kang, Jong-Son Lyu, Jin-Young Kang, Sang-Won Kang, Jin-Hyo Lee
1995 IEEE Electron Device Letters  
Abstfuct-Leakage current through the parasitic channel formed at the sidewall of the SO1 active region has been investigated by measuring the subthreshold I-V characteristics. Partially depleted (PD, -2500 A) and fully depleted (FD, -800 A) SO1 NMOS transistors of enhancement mode have been fabricated using the silicon direct bonding (SDB) technology. Isolation processes for the SO1 devices were LOCOS, LOCOS with channel stop ion implantation or fully recessed trench (FRT). The electron
more » ... ation of the parasitic channel is calculated by the PISCES IIh simulation. As a result, leakage current of the FD mode SO1 device with FRT isolation at the front and hack gate biases of 0 V was reduced to -PA and no hump was seen on the drain current curve.
doi:10.1109/55.790720 fatcat:gtlkhe6ngvgpxnlhmh7c4sdzym