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Hardware Pipelining of Repetitive Patterns in Processor Instruction Traces
Journal of Integrated Circuits and Systems
Dynamic partitioning is a promising technique where computations are transparently moved from a Gene- ral Purpose Processor (GPP) to a coprocessor during application execution. To be effective, the mapping of computations to the coprocessor needs to consider aggressive optimizations. One of the mapping opti- mizations is loop pipelining, a technique extensively studied and known to allow substantial performance improvements. This paper describes a technique for pipelining Megablocks, a type ofdoi:10.29292/jics.v8i1.373 fatcat:6fvot4onazgjbejixtutauyymq