Confession session: Learning from others mistakes

P. Abshire, A. Bermak, R. Berner, G. Cauwenberghs, S. Chen, J. B. Christen, T. Constandinou, E. Culurciello, M. Dandin, T. Datta, T. Delbruck, P. Dudek (+8 others)
2011 2011 IEEE International Symposium of Circuits and Systems (ISCAS)  
People rarely put in their papers the things that didn't work, the mistakes they made, and how they found out what went wrong. Such confessions can help others learn how to avoid similar mistakes. Twenty-six confessions were collected to form the bulk of this paper. Themes that arise are errors that result from not understanding the limitations of simulation tools in modeling physical reality, chip verification errors that result from lack of clear communication between designers, and projects
more » ... hat are considered in their own isolated environment of technical challenges rather than the broader context of their environment or application. 978-1-4244-9472-9/11/$26.00 ©2011 IEEE We hope that, if repeated, in future years other TCs will contribute in a more balanced manner. We know we are not alone in making mistakes! So, without further ado, here are this inaugural year's confessions. II. MISTAKES IN PLANNING Some confessions result from not considering a project fully in its planning stages. We are developing a suite of sensors for biosensing applications. The devices consist of the hybrid assembly of a CMOS die with micro-electromechanical systems (MEMS) structures (Dandin et al. 2009 ). The sensing functionality is achieved on the die with the aid of application-specific integrated circuits and the MEMS structures serve as support for the biological sample under study. The yield of the integration process (the postfabrication of MEMS structures on the CMOS die) has been unsatisfactory. This results from the small size of the dice (1.5x1.5mm 2 ) that are typically available for prototyping on multi-project runs. Handling these small chips is difficult, and most importantly, impedes the accurate transfer of lithographic patterns on top of the chip; the application of a uniform photoresist layer is not easy since the tinier the sample, the more likely that photoresist will exhibit a significant edge bead after the spin-coating step. The edge bead can take up a large fraction of the available surface area of the chip. This issue is even more pronounced when thick resists are used.
doi:10.1109/iscas.2011.5937774 dblp:conf/iscas/AbshireBBCCCCCDDDDEEILLTTZ11 fatcat:a5g777ijpzcc7aflwclvpnzwhm