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2010 53rd IEEE International Midwest Symposium on Circuits and Systems
The paper presents new results in the hardware implementation and optimization of recursive sequential and parallel algorithms using the known and a new model of a hierarchical finite state machine. Applicability and advantages of the proposed methods are confirmed through numerous examples of the designed hardware circuits that have been analyzed and compared. The results of experiments and FPGAbased prototyping demonstrate clearly that the proposed innovations enable the required hardwaredoi:10.1109/mwscas.2010.5548674 fatcat:wft566tfwbg63m2ecqtwa5og6u