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Frequency and voltage planning for multi-core processors under thermal constraints
2008
2008 IEEE International Conference on Computer Design
Clock frequency and transistor density increases have resulted in elevated chip temperatures. In order to meet temperature constraints while still exploiting the performance opportunities enabled by continued scaling, chip designers have migrated towards multi-core architectures. Multi-core architectures use multiple cores running at moderate clock frequencies to run several threads concurrently, which increases overall system throughput. In this work, we propose novel methods to find the
doi:10.1109/iccd.2008.4751902
dblp:conf/iccd/KadinR08
fatcat:zxzblz2yr5fvzgx3lxtyrocnpy