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Dynamically reducing pressure on the physical register file through simple register sharing
IEEE International Symposium on - ISPASS Performance Analysis of Systems and Software, 2004
Using register renaming and physical registers, modern microprocessors eliminate false data dependences from reuse of the instruction set defined registers (logical registers). High performance processors that have longer pipelines and a greater capacity to exploit instruction-level parallelism have more instructions in-flight and require more physical registers. Simultaneous multithreading architectures further exacerbate this register pressure. This paper evaluates two register sharing
doi:10.1109/ispass.2004.1291358
dblp:conf/ispass/TranNNDH04
fatcat:qx7t5ugjurcnpe4ohpd4h43l5e