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Based on the physical model of nanocrystal (NC) memories described in Part I, a systematic investigation of gate-stack engineering is presented, including high-κ control and tunneling oxides. The high-κ control oxide enables the effectiveoxide-thickness scaling without compromising the memory performance, owing to the low charging energy and large channel-control factor from the three-dimensional electrostatics. The high-κ tunneling oxide, on the other hand, improves the retentiondoi:10.1109/ted.2006.885678 fatcat:mbv4ezelfbfkpbwrl7un6zcxqy