Design Optimization of Metal Nanocrystal Memory—Part II: Gate-Stack Engineering

Tuo-Hung Hou, Chungho Lee, Venkat Narayanan, Udayan Ganguly, Edwin Chihchuan Kan
2006 IEEE Transactions on Electron Devices  
Based on the physical model of nanocrystal (NC) memories described in Part I, a systematic investigation of gate-stack engineering is presented, including high-κ control and tunneling oxides. The high-κ control oxide enables the effectiveoxide-thickness scaling without compromising the memory performance, owing to the low charging energy and large channel-control factor from the three-dimensional electrostatics. The high-κ tunneling oxide, on the other hand, improves the retention
more » ... s utilizing the asymmetric tunneling barrier more effectively away from the direct tunneling regime. Finally, with the optimization strategies introduced in both Parts I and II, a metal NC memory design with 1.0-V memory window, 13-µs programming, 2.5-µs erasing, and over 10-year retention time has been demonstrated at ±4-V operation, which highlights the potential of NC memories as the next-generation nonvolatile memory.
doi:10.1109/ted.2006.885678 fatcat:mbv4ezelfbfkpbwrl7un6zcxqy