SAT-Based Verification Methods and Applications in Hardware Verification [chapter]

Aarti Gupta, Malay K. Ganai, Chao Wang
2006 Lecture Notes in Computer Science  
Verification methods based on Boolean Satisfiability (SAT) have emerged as a promising alternative to BDD-based symbolic model checking methods. This paper provides a tutorial on various SAT-based verification methods we have developed for verifying large hardware designs. We focus separately on methods for finding bugs and for finding proofs for correctness properties, along with highlighting the many common themes that benefit these methods. We also describe practical experiences with these
more » ... thods implemented in our verification platform called VeriSol (formerly DiVer), which has been used successfully in industry practice.
doi:10.1007/11757283_5 fatcat:5kb2pmlvjvat5ljeei2fflzufa