Statistical simulation: Adding efficiency to the computer designer's toolbox

L. Eeckhout, S. Nussbaum, J.E. Smith, K. De Bosschere
2003 IEEE Micro  
system design is a timeconsuming complex process, and simulation is essential to overall design activity. Simulation occurs at many levels, from circuit to system, and at different degrees of detail as the design evolves. The designer's toolbox holds evaluation tools, often used in combination: each tool has different complexity, accuracy, and execution-time properties. Detailed models of register transfer activity typically conduct simulation at the microarchitecture level. These simulators
more » ... ck instructions and data on a per-cycle basis and typically provide detailed models for features such as instruction issue mechanisms, caches, load/store queues, and branch predictors, as well as their interactions. For input, microarchitecture simulators take sets of benchmark programs, including standard and companyproprietary suites. These benchmarks can each contain billions of dynamically executed instructions, and typical simulators run many orders of magnitude slower than real processors, producing a relatively long runtime for even a single simulation. However, processor simulation at such a detailed level is neither always appropriate, nor necessary. For example, early in the design process, while exploring the design space and determining the high-level microarchitecture, too much detail only gets in the way. The initial definition of a processor microarchitecture requires basic design decisions. These decisions involve tradeoffs related to basic cycle time and instructions per cycle; cache and predictor sizing; and performance/power. At this stage of the design process, detailed microarchitecture simulations of specific benchmarks aren't feasible. For one, the detailed simulator itself takes considerable time and effort to develop. Second, benchmarks restrict the application space under evaluation to the specific programs represented by the benchmarks. To study a fairly broad design space, the number of simulation runs can be quite large. Finally, highly accurate performance estimates are illusory anyway, given the knowable level of design detail. Similarly, for making system-level design decisions, where a processor (or several processors) might be combined with many other components, a very detailed simulation model is often unjustified or impractical. Even though the detailed processor microarchitecture might be known, the number of processors and the larger benchmark programs necessary for
doi:10.1109/mm.2003.1240210 fatcat:nith3o67vvcrjlvxg77wvqyzh4