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Instruction flow-based front-end throttling for power-aware high-performance processors
Proceedings of the 2001 international symposium on Low power electronics and design - ISLPED '01
We present a number of power-aware instruction front-end (fetch/decode) throttling methods for high-performance dynamically-scheduled superscalar processors. Our methods reduce power dissipation by selectively turning on and off instruction fetch and decode. Moreover, they have a negligible impact on performance as they deliver instructions just in time for exploiting the available parallelism. Previously proposed front-end throttling methods rely on branch prediction confidence estimation. Wedoi:10.1145/383082.383088 dblp:conf/islped/BaniasadiM01 fatcat:nbagrpjzqbdcjmkf4wlhuvuujq