Recent developments suggest both plausible fabrication techniques and viable architectures for building sublithographic Programmable Logic Arrays using molecular-scale wires and switches. Designs at this scale will see much higher defect rates than in conventional lithography. However, these defects need not be an impediment to programmable logic design at this scale. We introduce a strategy for tolerating defective crosspoints in PLA architecture. We develop a lineartime, greedy algorithm for

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... apping PLA logic around crosspoint defects. The mapping algorithm matches the PLA logic to the defect configuration of each device. We note that P-term fanin must be bounded to guarantee low overhead mapping and develop analytical guidelines for bounding fanin. We further quantify analytical and empirical mapping overhead rates. Including fanin bounding, our greedy mapping algorithm maps a large set of benchmark designs with 13% average overhead for random junction defect rates as high as 20%. iv Contents Acknowledgements iii Abstract iv Area Overhead Estimation Here we compute how large W , number of nanowires, should be for each design so that it can be successfully mapped to the physical nanoPLA. When matching the ith OR function we have |W | − i unmatched nanowires. Applying Equation 6.