Self-Timed Reconfigurable Controllers Design for Parallel Synchronization via Wagging 64 International Journal of Recent Trends in VLSI, Embedded Systems and Signal Processing Self-Timed Reconfigurable Controllers Design for Parallel Synchronization via Wagging

D Prajwala, P Suresh Babu
unpublished
Synchronization is an important issue in modern system design as systems-on-chips integrate more diverse technologies, operating voltages, and clock frequencies on a single substrate. This project is a methodology for the design and implementation of a self-timed reconfigurable control device suitable for a parallel cascaded flip-flop synchronizer based on a principle known as wagging, through the application of distributed feedback graphs. By modifying the endpoint adjacency of a common
more » ... of a common behavior graph via one-hot codes, several configurable modes can be implemented in a single design specification, thereby facilitating direct control over the synchronization time and the meantime between failures of the parallel master-slave latches in the synchronizer. This project includes a discussion of the reconfiguration protocol, and implementations of both a sequential token ring control device, and an interrupt subsystem necessary for reconfiguration, all simulated in UMC90-nm technology. The interrupt subsystem demonstrates operating frequencies between 505 and 818 MHz per module, with average power consumptions between 70.7 and 90.0μW.
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