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As microprocessors become faster and demand more bandwidth, the already limited scalability of a shared bus decreases even further. DICE, a shared-bus multiprocessor, utilizes cache only memory architecture (COMA) to effectively decrease the speed gap between modern high-performance microprocessors and the bus. DICE tries to optimize COMA for a shared-bus medium, in particular to reduce the detrimental effects of cache coherence and the"last memory block" problem on replacement. In this paper,doi:10.1006/jpdc.1998.1524 fatcat:fdu7qc55k5f2jazhvs5sbazdwi