Coherence and Replacement Protocol of DICE—A Bus-Based COMA Multiprocessor

Sangyeun Cho, Jinseok Kong, Gyungho Lee
1999 Journal of Parallel and Distributed Computing  
As microprocessors become faster and demand more bandwidth, the already limited scalability of a shared bus decreases even further. DICE, a shared-bus multiprocessor, utilizes cache only memory architecture (COMA) to effectively decrease the speed gap between modern high-performance microprocessors and the bus. DICE tries to optimize COMA for a shared-bus medium, in particular to reduce the detrimental effects of cache coherence and the"last memory block" problem on replacement. In this paper,
more » ... e present the coherence and replacement protocol of the DICE multiprocessor and its design trade-offs. We describe a four-state write-invalidate coherence protocol in detail. Replacement, which poses a unique overhead problem of COMA, requires that a victim block with ownership be relocated to a remote node in order not to discard the last cached memory block. We show that the relocation process can be efficiently implemented by using a temporary storage called relocation buffer and a priority-based selection algorithm. We present performance results that show a drastic reduction in global bus traffic compared to a traditional shared-bus multiprocessor architecture. 1999 Academic Press, Inc.
doi:10.1006/jpdc.1998.1524 fatcat:fdu7qc55k5f2jazhvs5sbazdwi