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2008 IEEE Symposium on VLSI Circuits
This paper describes a 16-Gb/s differential bidirectional I/O transceiver cell in an emulated 40nm DRAM process that has a fan-out of four inverter delay (FO4) of 45ps, resulting in a bit time that is only 1.4 FO4 delays long. The transceiver implements several techniques to achieve low jitter despite the slow process and constrained power consumption, including a quad rate clocking with closed-loop quadrature correction, a shared LC-PLL with an octagonal inductor in a three-metal process, anddoi:10.1109/vlsic.2008.4585979 fatcat:a5d6ipqimjdvdaf6j3svetu53q