A 16-Gb/s differential I/O cell with 380fs RJ in an emulated 40nm DRAM process

Nhat Nguyen, Yohan Frans, Brian Leibowitz, Simon Li, Reza Navid, Marko Aleksic, Fred Lee, Fredy Quan, Jared Zerbe, Rich Perego, Fari Assaderaghi
2008 2008 IEEE Symposium on VLSI Circuits  
This paper describes a 16-Gb/s differential bidirectional I/O transceiver cell in an emulated 40nm DRAM process that has a fan-out of four inverter delay (FO4) of 45ps, resulting in a bit time that is only 1.4 FO4 delays long. The transceiver implements several techniques to achieve low jitter despite the slow process and constrained power consumption, including a quad rate clocking with closed-loop quadrature correction, a shared LC-PLL with an octagonal inductor in a three-metal process, and
more » ... metal process, and a data-dependent regulator. The transceiver has measured random jitter of 380fs rms at the transmitter output and BER < 10 -14 while consuming 8mW/Gb/s.
doi:10.1109/vlsic.2008.4585979 fatcat:a5d6ipqimjdvdaf6j3svetu53q