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Design considerations for robustness with respect to variations and low power operations typically impose contradictory design requirements. Low power design techniques such as voltage scaling, dual-Vth etc. can have a large negative impact on parametric yield. In this paper, we propose a novel paradigm for low-power variationtolerant circuit design, which allows aggressive voltage scaling. The principal idea is to (a) isolate and predict the set ofpossible paths that may become critical underdoi:10.1109/iccad.2006.320025 fatcat:dxsq6wwpobex5oqrzjz7k2inrm