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Design of Image Recognition Accelerator Based on FPGA
2019
DEStech Transactions on Computer Science and Engineering
Based on the application of convolutional neural network (CNN) in the field of image recognition and the characteristics of a large number of computing requirements, this paper designs an accelerator based on SDSoC (Software-defined on-chip programmable system). The key parameters of the CNN training structure file and the selection of the appropriate excitation function ReLU (Rectifiedlinearunit) for training the convolutional neural network on the virtual machine are mainly modified. Finally,
doi:10.12783/dtcse/iciti2018/29175
fatcat:nm4ri4texfc23jz2shyvseqczm