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A fully associative, tagless DRAM cache
2015
Proceedings of the 42nd Annual International Symposium on Computer Architecture - ISCA '15
This paper introduces a tagless cache architecture for large in-package DRAM caches. The conventional die-stacked DRAM cache has both a TLB and a cache tag array, which are responsible for virtual-to-physical and physical-to-cache address translation, respectively. We propose to align the granularity of caching with OS page size and take a unified approach to address translation and cache tag management. To this end, we introduce cache-map TLB (cTLB), which stores virtual-to-cache, instead of
doi:10.1145/2749469.2750383
dblp:conf/isca/LeeKJYKJL15
fatcat:xtukcfzepnh65m6jx4jm2tweo4