The 'test model-checking' approach to the verification of formal memory models of multiprocessors [chapter]

Ratan Nalumasu, Rajnish Ghughal, Abdel Mokkedem, Ganesh Gopalakrishnan
1998 Lecture Notes in Computer Science  
We offer a solution to the problem of verifying formal memory models of processors by combining the strengths of model-checking and a formal testing procedure for parallel machines. We characterize the formal basis for abstracting the tests into test automata and associated memory rule safety properties whose violations pinpoint the ordering rule being violated. Our experimental results on Verilog models of a commercial split transaction bus demonstrates the ability of our method to effectively
more » ... debug design models during early stages of their development.
doi:10.1007/bfb0028767 fatcat:oj2aimybqfc43ad4lnohzfphie