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Scientific Application Performance on Candidate PetaScale Platforms
2007
2007 IEEE International Parallel and Distributed Processing Symposium
After a decade where HEC (high-end computing) capability was dominated by the rapid pace of improvements to CPU clock frequency, the performance of next-generation supercomputers is increasingly differentiated by varying interconnect designs and levels of integration. Understanding the tradeoffs of these system designs, in the context of high-end numerical simulations, is a key step towards making effective petascale computing a reality. This work represents one of the most comprehensive
doi:10.1109/ipdps.2007.370259
dblp:conf/ipps/OlikerCCILKSSSEG07
fatcat:2qwlvhvrwrbf7mhguaqs2jx64i