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Symbolic cover minimization of fully I/O specified finite state machines
1990
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Symbolic cover minimization is an important step within a well-known state-assignment technique for finite state machines (FSM's) 121. Currently, multiple-valued-input logic minimization techniques are used to find a minimum symbolic cover. The former problem, however, is computationally intractable, so heuristics are used. We show a simplified technique, based on an extension of the FSM minimization technique, which enables an efficient deterministic solution for fully I/O specified FSM's.
doi:10.1109/43.55214
fatcat:f2hjju6rjnbhbeyosqyr2u56ui