Wireless platforms: GOPS for cents and MilliWatts

F. Bacchini, J. Rabaey, A. Cox, F. Lane, R. Lauwereins, U. Ramacher, D. Witt
2005 Proceedings. 42nd Design Automation Conference, 2005.  
PANEL SUMMARY In recent years, data communication has overtaken voice as the main force behind the growth in wireless. With this has come a proliferation of standards ranging from wide area networks at one end of the spectrum to personal area networks on the other end. The opportunities offered by this truly ubiquitous connectivity are tremendous, and are leading to revolutionary chances in the way computer, communication, and consumer systems operatc and interact. Providing the necessary
more » ... ility to seamlessly interact with the multitude of emerging network models, as well as the muscle to support the demanding multimedia functionality in a mobile environment, presents some huge challenges to the developer of the wireless implementation platforms. The power budget of the mobile terminal is typically fixed by size considerations and operation time. Cost considerations further constrain the solution space. In response to these challenges, many solutions have been floated and experimented with ranging from multi-processor architectures, advanced DSPs, reconfigurable solutions and hardwired accelerators. While these innovations break new ground in the world of embedded architectures, many questions emerge such as efficiency, flexibility and programming model. This panel will presents a "bake-off" between a number of solutions that have emerged over the recent years. PANELISTS VIEWPOINTS Allan Cox, 3Plus I Technology, Inc. Implementing new voice, video and data functions in next generation systems, requires targe increases in computational "horsepower". However, mass consumption of mobile systems that include such functions depends on delivering this added horsepower, on a programmable platform, at no additional cost and with such efficiency that reduced power consumption extends battery life beyond today's limits. Performance saturation of conventional computing architectures and their associated power inefficiencies have driven multiprocessor architectures that can achieve these compute demands through concurrent operation. Nigh efficiencies can be achievable by implementation of heterogeneous multiprocessor architectures whose structures reflect the application characteristics and optimize for low area and power. Hierarchical scaling of compute element, processor, micro-interconnect and macrointerconnect are critical factors for success. Finally the smooth integration of a single programming model software scheme, within the hardware architecture can be made, such that familiar programming tools and techniques are reusable by the applications community Frank Lane, Flarion Technolgies, Inc. We are still in the infancy of broadband wireless access, and as such, we are seeing developments in algorithms, protocols, and standards evolve faster than hardware design cycles. For infrastructure, which typically have a multi-year product lifetime, the only alternative is to move to a reconfigurable platform. Such a platform, comprised of multiple processors, reconfigurable logic, and flexible interconnect, and the distributed processing which operate on it, provide a significant challenge to design, development, and verification.
doi:10.1109/dac.2005.193832 fatcat:drppi7vv2vbkzj7h2v5lkuznoe