A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf
.
A Multi–Alphabet Arithmetic Coding Hardware Implementation for Small FPGA Devices
2013
Journal of Electrical Engineering
Arithmetic coding is a lossless compression algorithm with variable-length source coding. It is more flexible and efficient than the well-known Huffman coding. In this paper we present a non-adaptive FPGA implementation of a multi-alphabet arithmetic coding with separated statistical model of the data source. The alphabet of the data source is a 256-symbol ASCII character set and does not include the special end-of-file symbol. No context switching is used in the proposed design which gives
doi:10.2478/jee-2013-0006
fatcat:cfggbcxpprfkfleeu2c247b4ni