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Synthesis of Reactive(1) Designs
[chapter]

2005
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Lecture Notes in Computer Science
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We consider the problem of synthesizing digital designs from their LTL specification. In spite of the theoretical double exponential lower bound for the general case, we show that for many expressive specifications of hardware designs the problem can be solved in time N 3 , where N is the size of the state space of the design. We describe the context of the problem, as part of the Prosyd European Project which aims to provide a property-based development flow for hardware designs. Within this

doi:10.1007/11609773_24
fatcat:o6loqezqzvhjnfyzyy2knypsya