An energy-aware scheduler for dynamically reconfigurable multi-core systems

Robin Bonamy, Sebastien Bilavarn, Fabrice Muller
2015 2015 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)  
This paper describes an energy-aware scheduling approach intended for use in heterogeneous multiprocessors supporting hardware acceleration with Dynamic and Partial Reconfiguration. Scheduler decisions rely on pragmatic power and energy models to map the load across cores and reconfigurable regions with regards to the actual power costs. Results on a multithreaded H.264/AVC profile decoder with three possible hardware functions on a Xilinx Zynq based platform report energy gains up to 44.1%
more » ... full software execution and 49.6% over static hardware / software execution, while ensuring realtime decoding requirement.
doi:10.1109/recosoc.2015.7238084 dblp:conf/recosoc/BonamyBM15 fatcat:s5qsva6dizhqfnrenrk7u2ur3u