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XTR Implementation on Reconfigurable Hardware
[chapter]
2004
Lecture Notes in Computer Science
Recently, Lenstra and Verheul proposed an efficient cryptosystem called XTR. This system represents elements of F * p 6 with order dividing p 2 − p + 1 by their trace over F p 2 . Compared with the usual representation, this one achieves a ratio of three between security size and manipulated data. Consequently very promising performance compared with RSA and ECC are expected. In this paper, we are dealing with hardware implementation of XTR, and more precisely with Field Programmable Gate Array
doi:10.1007/978-3-540-28632-5_28
fatcat:z4vw3quxkfhxzlqclf5q6nwbty