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A scalable and compact systolic architecture for linear solvers
2014
2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors
We present a scalable design for accelerating the problem of solving a dense linear system of equations using LU Decomposition. A novel systolic array architecture that can be used as a building block in scientific applications is described and prototyped on a Xilinx Virtex 6 FPGA. This solver has a throughput of around 3.2 million linear systems per second for matrices of size N=4 and around 80 thousand linear systems per second for matrices of size N=16. In comparison with similar work, our
doi:10.1109/asap.2014.6868658
dblp:conf/asap/OngFL14
fatcat:3j23w7boyffb7issoqhobvblei