Applying asynchronous techniques to a Viterbi Decoder design

L.E.M. Brackenbury
2001 IEE Seminar Low Power IC Design   unpublished
Q2001Thelnstitution of EledriCal Engineers. of arithmetic used in the PMU. Serial unary arithmetic has been adopted within the PMU. Here, all weights are held as a series of events in data-less FIFOs, with the data implicitly indicated by the state of the FIFO control elements. Two phase arithmetic is used so that the levels convey no meaning. However, an edge (or change of state from one control element to the next) indicates an event which is interpreted as a count of one. The basic unit of
more » ... The basic unit of replication in the PMU is a node pair due to the nature of the butterfly interconnection network between node outputs and node inputs. In this particular system there are 32 node pairs i.e. 64 nodes. The logic for a node pair is illustrated in figure 2. nous timing strategy has resulted in a novel design. The use of scaling, weight capping and normalisa-2/4
doi:10.1049/ic:20010008 fatcat:4dzzxdtiwzfvpgcjtmr3axc5ae