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A wide variety of computer architectures have been proposed that attempt to exploit parallelism at different granularities. For example, pipelined processors and multiple instruction issue processors exploit the fine-grained parallelism available at the machine instruction level, while shared memory multiprocessors exploit the coarse-grained parallelism available at the loop level. Using a registertransfer level simulation methodology, this paper examines the performance of a multiprocessordoi:10.1016/0167-8191(94)90003-5 fatcat:5owuiokm5bha5jdcjvqg7shnja