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Automatic verification of scheduling results in high-level synthesis
Proceedings of the conference on Design, automation and test in Europe - DATE '99
A method for the fully automatic equivalence verification of a design before and after the scheduling step of high-level synthesis is presented. The technique is applicable to the results of advanced scheduling methods like AFAP and DLS, which work on cyclic control flows, as well as to pipelined designs.doi:10.1145/307418.307449 fatcat:eutcqz53evgtnlvtj3zpktig6y