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Efficient use of limited available resources on an FPGA remains a crucial problem for synthesizing pipelined designs. Resource sharing addresses this challenge. In this paper, we propose resource sharing techniques that can be incorporated into an automated synthesis flow to generate pipelined designs. Given a synthesized pipelined design, we create a direct relationship between available time slack on modules and the multiplexing overhead due to sharing. This flexibility is maximally exploiteddoi:10.1145/1120725.1121019 dblp:conf/aspdac/MondalM05 fatcat:7r2dbz7n45aghj2lfenizw3nli