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Automatic performance model construction for the fast software exploration of new hardware designs
2006
Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems - CASES '06
Developing an optimizing compiler for a newly proposed architecture is extremely difficult when there is only a simulator of the machine available. Designing such a compiler requires running many experiments in order to understand how different optimizations interact. Given that simulators are orders of magnitude slower than real processors, such experiments are highly restricted. This paper develops a technique to automatically build a performance model for predicting the impact of program
doi:10.1145/1176760.1176765
dblp:conf/cases/CavazosDABOFT06
fatcat:qfuzosk6gfdcpb45mzzvbp7cea