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Robust high-performance low-power carry select adder
Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC
This paper proposes Dual Transition Skewed Logic (DTSL) based Carry Select Adder (CSA) suitable for processing units requiring low power and high performance with high noise immunity. We implemented 31-bit Carry Select Adders in three different logic styles: Dual Transition Skewed Logic (DTSL), Domino, and conventional static CMOS in TSMC 0.25um technology and compared them in terms of performance, power consumption and layout area. CSA using DTSL shows 36.7% and 17.7% improvements in powerdoi:10.1145/1119772.1119876 dblp:conf/aspdac/JeongR03 fatcat:66qxth72ijeezibpjhqcdwyjp4