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Multiple branch and block prediction
Proceedings Third International Symposium on High-Performance Computer Architecture
Accurate branch prediction and instruction fetch prediction of a microprocessor are critical to achieve high performance. For a processor which fetches and executes multiple instructions per cycle, an accurate and high bandwidth instruction fetching mechanism becomes increasingly important to performance. Unfortunately, the relatively small basic block size exhibited in many general-purpose applications severely limits instruction fetching. In order to achieve a high fetching rate for
doi:10.1109/hpca.1997.569645
dblp:conf/hpca/WallaceB97
fatcat:t2znawnzrzfgtakd36luw5cnq4