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In present work two new designs for single bit full adders have been presented using three transistors XOR gates. Adder having twelve transistors shows power consumption of 1274µW with maximum output delay of 0.2049ns. Power consumption and maximum output delay shows variation [1274 -141.77] µW & [0.2049 -0.4167] ns with varying supply voltage from [3.3 -1.8] V. Further, reverse body bias technique for power reduction has been applied to adder. Adder with reverse body bias shows powerdoi:10.5121/ijitcs.2012.2602 fatcat:5mggmucgabag5elufanljjtnku