A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf
.
A high-performance microarchitecture with hardware-programmable functional units
1994
Proceedings of the 27th annual international symposium on Microarchitecture - MICRO 27
This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Through a coupling of compile-time analysis routines and hardware synthesis tools, we automatically configure a given set of the hardware-programmable functional units (PFUs) and thus augment the base instruction set architecture so that it better meets the instruction set needs of each application. We refer to this new
doi:10.1145/192724.192749
fatcat:5b4xwjneyrbh3nbumgir5poecq