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Compiler optimizations for improving data locality
1994
Proceedings of the sixth international conference on Architectural support for programming languages and operating systems - ASPLOS-VI
In the past decade, processor speed has become significantly faster than memory speed. Small, fast cache memories are designed to overcome this discrepancy, but they are only effective when programs exhibit data locality. In this paper, we present compiler optimizations to improve data locality based on a simple yet accurate cost model. The model computes both temporal and spatial reuse of cache lines to find desirable loop organizations. The cost model drives the application of compound
doi:10.1145/195473.195557
dblp:conf/asplos/CarrMT94
fatcat:urxkfxttunevldf7xmo2py4wcq