Energy-Efficient Thread-Level Speculation

J. Renau, K. Strauss, L. Ceze, Wei Liu, S.R. Sarangi, J. Tuck, J. Torrellas
2006 IEEE Micro  
To speed up nonnumerical applications that are hard to parallelize, designers build sophisticated out-of-order processors with carefully tuned execution engines and memory subsystems. Unfortunately, these systems tend to have highly complex designs and yield diminishing performance returnsmotivating the search for design alternatives. One such alternative is thread-level speculation (TLS) on a chip multiprocessor (CMP). CMPs are attractive because they are more energy efficient, more scalable,
more » ... nd less complex than wide-issue superscalar processors. With TLS, they can also execute in parallel challenging sequential codes, such as SPECint. TLS partitions hard-to-analyze applications into tasks that the processors optimistically execute in parallel, hoping to avoid any cross-task dependence violation. Special hardware support monitors the tasks' data accesses and detects runtime violations. If such a violation occurs, the hardware transparently rolls back the incorrect tasks and, after repairing the state, restarts them. The "Principles of Thread-Level Speculation" sidebar describes TLS foundations in more detail. Although a TLS CMP offers major benefits, many contend that its energy efficiency is too low to seriously challenge conventional processors. The rationale is that aggressive speculative execution is not the best course when energy and power consumption are a processor's primary constraints. We argue otherwise, and have identified simple energy-saving optimizations that make a TLS CMP an attractive option for highperformance, power-constrained processor design, even running SPECint codes. Our TLS CMP design relies on an efficient microarchitecture with out-of-order task spawning and a novel TLS compiler. When we evaluated this design, we found that TLS's energy consumption remained modest and that our TLS CMP provided a better energyperformance trade-off than a wider issue superscalar processor. 1,2 Reducing energy consumption Enhancing an N-issue superscalar to make it a CMP with several N-issue cores and TLS support naturally increases energy consumption.
doi:10.1109/mm.2006.11 fatcat:zd2zg2xfgrenboie4btmi52hhq